AUTOMATED SYNTHESIS OF INTEGRATED CIRCUITS FOR VISION

Georges QUÉNOT, Ivan KRALJIC*, Bertrand ZAVIDOVIQUE**

Object: The purpose of this research is to develop tools allowing fast and automatic generation of integrated circuits (or chip sets) dedicated to implement, on demand and in a compact and economic way, real time vision systems. This work is carried out in cooperation with the Perception System Laboratory from the DGA/ETCA (PhD thesis Ivan Kraljic) as part of their Data-Flow Functional Computer project.

Content: The chosen approach is called emulation / derivation. It is articulated around the Data-Flow Functional Computer which is a massively parallel data-flow machine (1024 processors within an 8 x 8 x 16 cubic mesh network) that processes on the fly and in real time digital video streams and which is programmed using a functional language (FP-like). The data-flow execution mode has been chosen because it fits very well the emulation / derivation approach.

During the emulation phase, the user may develop and debug its applications on the Data-Flow Functional Computer in an interactive way and in real conditions. He writes a program in a functional language tailored to the architecture: every primitive function of this language corresponds to an operator implementable on a processor and every functional form (composition, construction) corresponds to a combination of operators (serial, parallel) as a data-flow graph. Figure 1 shows a very simple edge point detector example. The D(n,p) operator is parameterizable and provides as output a pixel flow shifted by n lines and p columns relatively to its input flow. The THR(v) operator performs a thresholding relatively to a parameter. The SUB, ABS and MAX operators perform simple arithmetic operations on data-flows. Figure 2 shows the corresponding operator data-flow graph and Figure 3 shows how such a graph may be placed and routed over a network of data-flow processors. Figure 4 shows the Data-Flow Functional Computer physical implementation. Figure 5 shows the emulation result as it can be seen in real-time on the monitors of the Data-Flow Functional Computer for a more complex application (defect detector within a regular texture).

The derivation consists in extracting a VLSI circuit description from an application emulated on the Data-Flow Functional Computer. The data-flow / functional approach guarantees that is is possible and efficiently feasible. The circuit description is a netlist of electronic components. A description is obtained for every used operator by simplifying the data-flow processor's one while taking into account the actually used resources. These descriptions are then merged according to the operator graph. Figure 6 shows a two-chip set that implements the emulated defect detector.

Situation: Current studies aim at improving the performance and generality of the tools in order to be able to handle more important and more various applications. New vision applications are also being developped.

Figures (postscript, 1574105 bytes).

References
(1) De la programmation fonctionnelle au traitement d'images temps réel, Jocelyn S. Sérot, Georges M. Quénot et Bertrand Zavidovique,. Technique et Science Informatiques 14(7), pp 839-865, Sept. 1995. Résumé, Abstract.
(2) Retargeting Field-Programmable Operator Arrays, [2431109 bytes] Ivan C. Kraljic, Georges M. Quénot and Bertrand Zavidovique, Third Canadian Workshop on Field-Programmable Devices, Montreal, Quebec, May 1995. Abstract.
(3) From Real-Time Emulation to ASIC Integration for Image Processing Applications, [424814 bytes] Ivan C. Kraljic, Georges M. Quénot and Bertrand Zavidovique, 8th Annual IEEE Intl. ASIC Conference, Austin, Texas, 18-22 September 1995. Abstract.
(4) High level synthesis by systematic derivation of vision automata from emulation results, Ivan C. Kraljic, Georges M. Quénot and Bertrand Zavidovique, In G. Saucier and A. Mignotte, editors, Logic and Architecture Synthesis: State of the Art and Novell Approaches, pages 300-306. Chapman & Halll, 1995. Abstract.
(5) Expérimentation en Architecture de Machines pour la Perception, [13108816 octets], version compressée gzip [4515409 octets], Georges M. Quénot, Habilitation à Diriger des Recherches, LIMSI, Orsay, 18 novembre 1998.

* Laboratoire Système de Perception, DGA/ETCA
** Institut d'Électronique Fondamentale, Université d'Orsay Paris XI